1. Field of the Invention
The present invention relates to the field of generating clock signals for semiconductor devices, and in particular, to distributing a reference clock signal to a large number of devices.
2. Discussion of the Prior Art
Modern high speed electronic systems require a number of semiconductor chips to communicate in time with a high speed clock. Clock distribution then becomes a serious engineering concern. A high speed clock, operating at the frequency of the data communication, must be delivered to each device. In the case of a synchronous memory base system, this can be thousands of devices. At present, 100 MHz clock rates, clock distribution requires considerable power, generates a large noise pulse due to the large number of common switching devices and radiates large amounts of energy which may cause radio interference.
U.S. Pat. No. 5,122,693 is directed to a clock distribution system which uses a separate power supply to power an internal clock driver on a semiconductor logic device.
In addition, at 100 MHz clock rates, the problem of clock distribution exists also within the chip being clocked. As the clock, sampled at the chip's clock input, is distributed throughout the chip, the delays are encountered and the clock may arrive at different parts of the chip at different times, and in any event, considerably later than the time it was first sampled. The problem of clock redistribution within the chip can be alleviated with some degree through the use of a feedback loop.
U.S. Pat. No. 5,204,555 and Japanese reference 64-15820 disclose such feedback loops. In this technique, a regenerated clock is compared to a reference clock and a correction is applied to the regenerated clock so that it has the same phase as the reference clock. To use this technique in a chip, a regenerated clock can be derived from a reference clock with the correction being derived by comparing the regenerated clock to the reference clock. The feedback of the regenerated clock to the clock reference is achieved with a phase locked loop. It is possible in this system to have the frequency of the reference clock larger or smaller than the frequency of the regenerated clock.
There is a need, therefore, for a system for distributing an external clock signal to a large number of devices that are communicating together.